How the family is organised
“ESP32” is a family name, not a part number. The suffix after it tells you which line a chip belongs to, and the line tells you what trade-off Espressif made:
| Line | What it optimises for | Members |
|---|---|---|
| No suffix / S | General purpose and multimedia — most GPIO, displays, cameras, USB | ESP32, S2, S3, S31 |
| C | Cost and power. Small packages, modern radios, lowest prices | C2, C3, C5, C6, C61 |
| H | Ultra-low power mesh. No Wi-Fi at all | H2, H21, H4 |
| P | Application performance. No radio at all | P4 |
| E | Radio only — a co-processor for a host CPU | E22 |
A second, orthogonal split matters just as much. The original ESP32, the S2 and the S3 use Espressif’s licensed Xtensa cores. Every part designed after them — the whole C, H, P and E series, and the new S31 — uses RISC-V. In practice this rarely affects application code, because ESP-IDF abstracts it, but it does affect toolchains, assembly-level optimisation and the availability of third-party runtimes.
Complete comparison
| Variant | ISA | Cores | Clock | SRAM | Radios | GPIO | USB | Sleep | Status | From |
|---|---|---|---|---|---|---|---|---|---|---|
| ESP32 | Xtensa | 2 + LP | 240 MHz | 520 KB | Wi-Fi 4 + BT Classic/LE | 34 | — | ~10 µA | Production | $1.50 |
| ESP32-S2 | Xtensa | 1 + LP | 240 MHz | 320 KB + 16 KB RTC | Wi-Fi 4 only | 43 | OTG Full Speed | ~5–7 µA | Production | $1.25 |
| ESP32-S3 | Xtensa | 2 + LP | 240 MHz | 512 KB + 16 KB RTC | Wi-Fi 4 + BLE 5 | 45 | OTG Full Speed | ~7 µA | Production | $1.85 |
| ESP32-S31 | RISC-V | 2 + LP | 320 MHz | 512 KB | Wi-Fi 6 + BT 5.4 + 802.15.4 + 1 GbE | 60 | OTG | Not yet published | Production | $3.80 |
| ESP32-C2 | RISC-V | 1 | 120 MHz | 272 KB | Wi-Fi 4 + BLE 5 | 14 | Serial/JTAG | <8 µA | Production | $1.00 |
| ESP32-C3 | RISC-V | 1 | 160 MHz | 400 KB | Wi-Fi 4 + BLE 5 | 22 | Serial/JTAG | ~5 µA | Production | $1.00 |
| ESP32-C5 | RISC-V | 1 + LP | 240 MHz | 384 KB + 16 KB LP | Dual-band Wi-Fi 6 + BLE 5 + 802.15.4 | 29 | Serial/JTAG | ~12 µA | Production | $2.50 |
| ESP32-C6 | RISC-V | 1 + LP | 160 MHz | 512 KB + 16 KB LP | Wi-Fi 6 + BLE 5.3 + 802.15.4 | 30 | Serial/JTAG | 7 µA | Production | $1.85 |
| ESP32-C61 | RISC-V | 1 + LP | 160 MHz | 320 KB + 4 KB LP | Wi-Fi 6 + BLE 5 | 30 | Serial/JTAG | ~10 µA | Production | $1.46 |
| ESP32-H2 | RISC-V | 1 + LP | 96 MHz | 320 KB + 4 KB LP | BLE 5 + 802.15.4 (no Wi-Fi) | 19 | Serial/JTAG | 7 µA | Production | $1.39 |
| ESP32-H21 | RISC-V | 1 + LP | 96 MHz | 320 KB + 128 KB ROM | BLE 5 + 802.15.4 (no Wi-Fi) | 19 | Serial/JTAG | 5 µA | Sampling | — |
| ESP32-H4 | RISC-V | 2 + LP | 96 MHz | 384 KB (expandable PSRAM) | BLE 5.4 + 802.15.4 (no Wi-Fi) | 35 | OTG | ~7 µA | Sampling | — |
| ESP32-P4 | RISC-V | 2 + LP | 400 MHz | 768 KB L2MEM + 32 KB LP | None (wired / companion radio) | 55 | OTG High Speed | ~25 µA | Production | $4.00 |
| ESP32-E22 | RISC-V | 2 + LP | 500 MHz | 1 MB | Tri-band Wi-Fi 6E + BT Classic/LE 5.4 | 30 | Host | Host-managed | Co-processor | — |
Cores counts high-performance cores; “+ LP” means a separate low-power core or ULP coprocessor is also present. USB distinguishes real OTG (which can implement USB device classes) from a Serial/JTAG peripheral (which cannot) — see Specifications. From is Espressif's published reference sample price for the cheapest orderable part number in the series and excludes flash and PSRAM options. Sleep currents are typical values, some estimated rather than characterised.
The lineup, by line
The original and the S-series
General-purpose and multimedia parts. The original ESP32 and the S-series use Espressif's Xtensa cores; the brand-new S31 moves the line to RISC-V. This is where you go for lots of GPIO, displays, cameras and USB.
ESP32
ProductionThe original. Dual-core, Bluetooth Classic, Ethernet MAC.
- CPUDual-core Xtensa LX6
- Clock80–240 MHz
- SRAM520 KB
- RadioWi-Fi 4 + BT Classic/LE
- GPIO34
- Sleep~10 µA
ESP32-S2
ProductionWi-Fi only, native USB, lots of pins.
- CPUSingle-core Xtensa LX7
- Clock40–240 MHz
- SRAM320 KB + 16 KB RTC
- RadioWi-Fi 4 only
- GPIO43
- Sleep~5–7 µA
ESP32-S3
ProductionThe multimedia and edge-AI workhorse.
- CPUDual-core Xtensa LX7 with 128-bit SIMD
- Clock40–240 MHz
- SRAM512 KB + 16 KB RTC
- RadioWi-Fi 4 + BLE 5
- GPIO45
- Sleep~7 µA
ESP32-S31
ProductionEverything, in one part. RISC-V, Wi-Fi 6, gigabit Ethernet.
- CPUDual-core RISC-V with MMU, one core with a 128-bit SIMD data path
- ClockUp to 320 MHz (6.86 CoreMark/MHz)
- SRAM512 KB
- RadioWi-Fi 6 + BT 5.4 + 802.15.4 + 1 GbE
- GPIO60
- SleepNot yet published
The C-series
Cost- and power-optimised RISC-V parts. Small packages, small pin counts, modern radios and the lowest prices in the family. The volume workhorses for connected sensors and appliances.
ESP32-C2
ProductionThe floor. Minimal, tiny, cheapest in the family.
- CPUSingle-core RISC-V
- Clock20–120 MHz
- SRAM272 KB
- RadioWi-Fi 4 + BLE 5
- GPIO14
- Sleep<8 µA
ESP32-C3
ProductionThe dependable dollar chip.
- CPUSingle-core RISC-V
- Clock40–160 MHz
- SRAM400 KB
- RadioWi-Fi 4 + BLE 5
- GPIO22
- Sleep~5 µA
ESP32-C5
ProductionThe only ESP32 that speaks 5 GHz.
- CPUSingle high-performance RISC-V core
- Clock40–240 MHz
- SRAM384 KB + 16 KB LP
- RadioDual-band Wi-Fi 6 + BLE 5 + 802.15.4
- GPIO29
- Sleep~12 µA
ESP32-C6
ProductionThe modern default. Wi-Fi 6, Thread, Zigbee, PSA L2.
- CPUSingle high-performance RISC-V core
- Clock40–160 MHz
- SRAM512 KB + 16 KB LP
- RadioWi-Fi 6 + BLE 5.3 + 802.15.4
- GPIO30
- Sleep7 µA
ESP32-C61
ProductionWi-Fi 6 on a budget.
- CPUSingle-core RISC-V
- Clock40–160 MHz
- SRAM320 KB + 4 KB LP
- RadioWi-Fi 6 + BLE 5
- GPIO30
- Sleep~10 µA
The H-series
Wi-Fi removed on purpose. Bluetooth LE plus 802.15.4 for Thread, Zigbee and Matter, tuned for single-digit microamp sleep currents and years of battery life.
ESP32-H2
ProductionMesh specialist. No Wi-Fi, by design.
- CPUSingle-core RISC-V
- Clock32–96 MHz
- SRAM320 KB + 4 KB LP
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- GPIO19
- Sleep7 µA
ESP32-H21
SamplingThe H2, refined. 5 µA and 20 dBm.
- CPUSingle-core RISC-V
- ClockUp to 96 MHz
- SRAM320 KB + 128 KB ROM
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- GPIO19
- Sleep5 µA
ESP32-H4
SamplingDual-core low power with Bluetooth 5.4.
- CPUDual-core RISC-V
- ClockUp to 96 MHz
- SRAM384 KB (expandable PSRAM)
- RadioBLE 5.4 + 802.15.4 (no Wi-Fi)
- GPIO35
- Sleep~7 µA
The P-series
The radio removed instead. Raw application performance, MIPI display and camera interfaces, hardware video codecs and high-speed USB. Pair one with a C-series chip for connectivity.
The E-series
Not a microcontroller. A radio co-processor that hangs off a Linux host over PCIe, SDIO or USB and takes over the entire Wi-Fi and Bluetooth stack.
What the table does not tell you
A specification table flattens some genuinely important distinctions. Four worth knowing before you commit to a part:
“USB” means three different things. The S2 and S3 have real USB OTG, but only at Full Speed (12 Mbps). The P4 has a High Speed controller (480 Mbps) and a Full Speed one and a serial/JTAG unit. Most C and H parts have only a USB Serial/JTAG peripheral — excellent for flashing and debugging without an external adapter, useless for implementing a USB device class. The original ESP32 has no USB at all.
“Hardware ECC” is not one feature. The C6 has a genuinely separate ECC accelerator block that measurably speeds up ECDSA signing and ECDH. The S3 is also marked as having ECC, but its operations run through the general-purpose bignum unit. Both get a tick in a comparison table; their performance differs by an order of magnitude. Details are in Specifications → security .
Deep-sleep figures are not equally trustworthy. Some are characterised datasheet values; others, particularly for the newest parts, are Espressif estimates extrapolated from similar silicon. Treat single-microamp differences between chips as noise until you measure your own board.
Announced is not available. Two of the fourteen parts here — the H21 and the H4 — are sampling rather than in volume production, and the E22 is not a microcontroller you can design in alone. The status badge on each row reflects this.
Also in the family, but not an ESP32
Three part numbers cause regular confusion:
- ESP8266 — the 2014 predecessor. Single Tensilica L106 core, 160 KB RAM, Wi-Fi only, no Bluetooth. Still sold and still supported, but there is no good reason to start a new design on it when the C2 and C3 cost the same and are dramatically more capable.
- ESP8684 — this is an ESP32-C2. Espressif sells the flash-integrated version of the C2 die under the ESP8684 name, which is why the C2 appears to have no in-package flash while ESP8684 modules clearly do.
- ESP8685 — likewise an ESP32-C3 variant sold under a different part number.
The naming is a historical artefact of how the parts were positioned commercially, not a difference in silicon family. See Boards & modules for the full decoder.
Every variant in detail
One page per SoC, each with the full specification, what it is genuinely good at and where it falls down.
ESP32
ProductionThe original. Dual-core, Bluetooth Classic, Ethernet MAC.
- CPUDual-core Xtensa LX6
- RadioWi-Fi 4 + BT Classic/LE
- SRAM520 KB
- GPIO34
ESP32-S2
ProductionWi-Fi only, native USB, lots of pins.
- CPUSingle-core Xtensa LX7
- RadioWi-Fi 4 only
- SRAM320 KB + 16 KB RTC
- GPIO43
ESP32-S3
ProductionThe multimedia and edge-AI workhorse.
- CPUDual-core Xtensa LX7 with 128-bit SIMD
- RadioWi-Fi 4 + BLE 5
- SRAM512 KB + 16 KB RTC
- GPIO45
ESP32-S31
ProductionEverything, in one part. RISC-V, Wi-Fi 6, gigabit Ethernet.
- CPUDual-core RISC-V with MMU, one core with a 128-bit SIMD data path
- RadioWi-Fi 6 + BT 5.4 + 802.15.4 + 1 GbE
- SRAM512 KB
- GPIO60
ESP32-C2
ProductionThe floor. Minimal, tiny, cheapest in the family.
- CPUSingle-core RISC-V
- RadioWi-Fi 4 + BLE 5
- SRAM272 KB
- GPIO14
ESP32-C3
ProductionThe dependable dollar chip.
- CPUSingle-core RISC-V
- RadioWi-Fi 4 + BLE 5
- SRAM400 KB
- GPIO22
ESP32-C5
ProductionThe only ESP32 that speaks 5 GHz.
- CPUSingle high-performance RISC-V core
- RadioDual-band Wi-Fi 6 + BLE 5 + 802.15.4
- SRAM384 KB + 16 KB LP
- GPIO29
ESP32-C6
ProductionThe modern default. Wi-Fi 6, Thread, Zigbee, PSA L2.
- CPUSingle high-performance RISC-V core
- RadioWi-Fi 6 + BLE 5.3 + 802.15.4
- SRAM512 KB + 16 KB LP
- GPIO30
ESP32-C61
ProductionWi-Fi 6 on a budget.
- CPUSingle-core RISC-V
- RadioWi-Fi 6 + BLE 5
- SRAM320 KB + 4 KB LP
- GPIO30
ESP32-H2
ProductionMesh specialist. No Wi-Fi, by design.
- CPUSingle-core RISC-V
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- SRAM320 KB + 4 KB LP
- GPIO19
ESP32-H21
SamplingThe H2, refined. 5 µA and 20 dBm.
- CPUSingle-core RISC-V
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- SRAM320 KB + 128 KB ROM
- GPIO19
ESP32-H4
SamplingDual-core low power with Bluetooth 5.4.
- CPUDual-core RISC-V
- RadioBLE 5.4 + 802.15.4 (no Wi-Fi)
- SRAM384 KB (expandable PSRAM)
- GPIO35
ESP32-P4
ProductionThe performance part. MIPI, H.264, high-speed USB, no radio.
- CPUDual-core RISC-V with FPU and AI extensions
- RadioNone (wired / companion radio)
- SRAM768 KB L2MEM + 32 KB LP
- GPIO55
ESP32-E22
Co-processorA tri-band Wi-Fi 6E radio for a Linux host.
- CPUDual-core RISC-V (radio co-processor architecture)
- RadioTri-band Wi-Fi 6E + BT Classic/LE 5.4
- SRAM1 MB
- GPIO30