Specifications

Full comparison

Cores counts high-performance cores; “+ LP” means a separate low-power core or ULP coprocessor is also present. USB distinguishes real OTG (which can implement USB device classes) from a Serial/JTAG peripheral (which cannot) — see Specifications. From is Espressif's published reference sample price for the cheapest orderable part number in the series and excludes flash and PSRAM options. Sleep currents are typical values, some estimated rather than characterised.

CPU and memory architecture

Instruction sets

Three CPU architectures appear across the family, and the split is chronological rather than functional.

For application code written against ESP-IDF, the ISA is mostly invisible. It matters in four places: hand-written assembly and intrinsics, third-party runtime availability (RISC-V generally has broader support in newer toolchains), debugging with external probes, and the fact that the RISC-V parts can carry small low-power RISC-V coprocessors that share the same toolchain as the main core.

Cores and coprocessors

The distinction between an ULP coprocessor and an LP core is worth understanding because it determines what your device can do while it is asleep.

SRAM and external memory

On-chip SRAM is the number that constrains you, and the headline figure always overstates what you get: the Wi-Fi and Bluetooth stacks consume a substantial slice, and on several parts the memory is split into regions with different access rules.

Two practical notes. PSRAM is not SRAM — it sits behind a cache over a serial bus, so access is slower and latency is less predictable; do not put interrupt-critical data there. And on some parts flash and PSRAM share a controller and contend for bandwidth; the S31 explicitly supports simultaneous access, which is a real advantage for display work.

Radios

Wi-Fi

The Wi-Fi 6 benefit for IoT is Target Wake Time and OFDMA, not throughput. TWT lets a device negotiate long sleep windows with the access point instead of waking for every beacon; OFDMA lets the AP service many clients per transmission opportunity, which is what makes congested networks tolerable.

Bluetooth

Only three parts have Bluetooth Classic: the original ESP32, the S31 and the E22. If you need A2DP audio, HFP or SPP, those are your options. Everything else is LE only.

IEEE 802.15.4 — Thread and Zigbee

Present on: C5, C6, H2, H21, H4, S31. Absent from: ESP32, S2, S3, C2, C3, C61, P4, E22.

Having the radio is necessary but not sufficient. Thread and Zigbee are network layers above it, and Matter is an application layer above them. Espressif provides certified stacks via ESP-IDF and ESP-Matter; the C6 additionally holds Thread 1.4 interoperability certification.

Multi-radio coexistence

On parts with more than one radio, the radios generally time-slice rather than operate genuinely concurrently. Wi-Fi, Bluetooth and 802.15.4 all share the 2.4 GHz front end on the C5, C6 and S31. This is managed transparently by ESP-IDF’s coexistence layer, but it caps aggregate throughput and adds latency jitter. A device acting as both a Wi-Fi station and a Thread router will not achieve the datasheet figures for both simultaneously.

Peripheral detail

USB — three different things called USB

This is the most commonly misread row in any ESP32 comparison table.

A USB Serial/JTAG peripheral is genuinely useful — it lets you flash and debug over a single USB cable with no CP2102 or CH340 on the board — but it is a fixed-function device. You cannot use it to present a HID keyboard, a mass-storage volume or a MIDI interface. If your product needs to be a USB device, you need OTG, which means an S2, S3, H4, S31 or P4.

UART

All parts share a 5 MBaud maximum on their general-purpose UART controllers, limited by the APB clock and internal division. Hardware flow control (RTS/CTS) is available on all general-purpose controllers. IrDA is supported on the ESP32, S2, S3, C3, C6 and P4. LP-UART, which operates on RTC clock sources at lower baud rates while the main core sleeps, is available on the C5, C6 and P4.

I2C

Slave mode is available on all general-purpose controllers except the ESP32-C2, which is master-only. If your design needs the ESP32 to be addressed by another controller over I2C, rule out the C2.

SPI

Controllers split into flash/PSRAM-dedicated (SPI0/SPI1) and general-purpose (SPI2/SPI3).

These are hardware controller maximums. Achievable clocks depend on whether the pins are routed through the GPIO matrix or use direct IO muxing (the matrix costs you speed), plus PCB layout and pull-up choices.

I2S — audio

RMT — the addressable-LED peripheral

RMT was designed for infrared remote control, but its flexible pulse timing made it the standard way to drive WS2812/NeoPixel strips, one-wire sensors like the DS18B20, and any software-defined precision timing.

Three things follow from this table:

1. The C2 and C61 have no RMT at all. No hardware IR, no clean NeoPixel driving, no DS18B20 without bit-banging. This is the single most under-advertised limitation of those two parts.
2. Only the S3 has RMT DMA. This decouples LED transmission from interrupt latency. On every other chip, a long addressable-LED chain can visibly glitch when the Wi-Fi radio delays an interrupt. If you are building anything with more than a short LED strip, this is a real argument for the S3.
3. Memory block size is 64 bytes per channel on the ESP32 and S2, 48 bytes on the S3/C3/C6/H2 generation, which caps how many RMT symbols fit before the driver borrows from an adjacent channel.

Other notable peripherals

Power and sleep

The ESP32-H21’s on-chip DC-DC converter is worth singling out, because it improves the term that usually matters most for mesh devices: receive current, quoted at around 8.2 mA. A Thread router that keeps its receiver on to relay neighbours’ traffic spends most of its life in RX, where a 2 µA difference in deep sleep is irrelevant.

Security and cryptography

Hardware accelerator matrix

Two ticks that are not the same tick

Similarly, “Digital Signature (ECDSA)” means a dedicated ECDSA_DS peripheral with the private key held in an eFuse block, inaccessible to software. That is verified on the C5, C61, H2, H4, P4 and S31. The C6, despite similar marketing language, has only the RSA-flavoured Digital Signature peripheral.

The C6 and the post-quantum wrinkle

The C6’s ECC accelerator covers NIST curves only, not Curve25519. Measured X25519 point multiplication takes about 121 ms whether the accelerator is on or off. That has a direct consequence for the hybrid post-quantum key exchange that both NIST and BSI guidance recommend: on a C6, the classical X25519 half of an X25519 + ML-KEM hybrid can cost more time than the entire ML-KEM-1024 encapsulation. A scheme chosen for regulatory alignment can end up slower than the post-quantum-only alternative it was meant to hedge.

No current embedded MCU accelerates ML-KEM or ML-DSA in hardware. Post-quantum cryptography on ESP32 is a software exercise, available through wolfSSL/wolfCrypt, liboqs and similar libraries. The P4 is the best platform for it on raw performance (400 MHz, 768 KB SRAM, DPA-resistant AES); the C6 is the best on security architecture (PSA L2, ESP-TEE); the S31 may supersede both once characterised.

Known advisory

Longevity commitments

Espressif publishes availability commitments, which matter for products with long service lives:

Note that several original ESP32 part numbers are marked NRND (not recommended for new designs) even though the family as a whole is committed. Always check the specific part number, not just the chip family, and read the errata sheet for your silicon revision.