ESP32Overview

Sources & Method

Where every number on this site came from, how it was verified, which claims are vendor marketing rather than measurement, and where the published documentation contradicts itself.

Method

Everything on this site was compiled and cross-checked in September 2026. The approach was:

  1. Prefer primary sources. Specifications come from Espressif’s own product pages, the SoC and module product selectors, the ESP-Techpedia board-selection comparison, and the series datasheets on documentation.espressif.com.
  2. Prices are Espressif’s own published figures. Every price on the pricing page is Espressif’s “sample price for reference” as displayed on its product selector, scraped and transcribed rather than estimated. Third-party board prices are street prices and clearly marked as approximate.
  3. Flag status honestly. Each variant carries a production status. Announced is not available; sampling is not volume production. The ESP32-C5 — announced 2022, in mass production 2025 — is why this matters.
  4. Separate measurement from marketing. Where a vendor claim is a specification rather than a characterised number, or an estimate extrapolated from similar silicon, it is labelled as such.
  5. Record disagreements rather than silently picking one. See the discrepancies section below.

Primary sources

Espressif product and specification pages

Espressif technical documentation

Corporate history

Software ecosystem

Community and secondary sources

Used for cross-checking, for peripheral-level detail that datasheet summaries omit, and for third-party board information. Content from these sources has been paraphrased and independently reorganised.

  • artkeller/ESP32Features (licensed CC-BY-4.0 ) — a datasheet-derived comparison covering all fourteen variants. This was the most useful single secondary source for the Specifications page : USB speed classes, UART/I2C/SPI/I2S limits, RMT channel architecture and DMA support, deep-sleep memory behaviour, and the hardware cryptography matrix. Attribution is required by its licence and gratefully given.
  • espboards.dev — cross-family comparison and a catalogue of third-party development boards.
  • atomic14.com/esp32/boards — third-party board and display board comparisons, including street pricing.
  • Vendor product pages for third-party hardware: Adafruit, Seeed Studio, LilyGO, Waveshare, M5Stack.
  • The ECC-accelerator measurements referenced on the specifications page — roughly 7× ECDSA signing and 16–18× ECDH speedup on the ESP32-C6 with the accelerator enabled, and no measurable X25519 speedup — originate from independent controlled hardware testing published by the community, notably NIkir0LL/lacert , rather than from vendor documentation.

Known discrepancies in published sources

Where sources disagree, this site records the disagreement rather than choosing silently.

ESP32-P4 clock speed. Espressif’s product page states 400 MHz; some datasheet revisions and comparison tables state 360 MHz. The difference appears to track silicon revisions, with the higher figure applying to later revisions such as v1.3. Espressif publishes the P4 as two related documents — a base series datasheet and a chip-revision-specific one — so confirm which revision you are ordering. This site quotes 400 MHz and notes the discrepancy on the P4 page .

ESP32-H4 memory and USB. Espressif’s board-selection table lists 384 KB of SRAM; other summaries list 320 KB. The same table credits the H4 with USB OTG, which some secondary sources dispute. No standalone H4 series datasheet PDF was publicly indexed at the time of writing, so these figures come from comparison tables rather than a characterised datasheet. Flagged as provisional on the H4 page .

ESP32 (original) deep-sleep current. Published figures range from ~10 µA to ~100 µA depending on which power domains and wake sources are assumed. This site uses ~10 µA as the typical minimum-configuration figure, but board-level current will normally be much higher.

ESP32-C6 ECC and ECDSA. Espressif’s marketing language for the C6 mentions ECDSA capability, but its own security overview does not document a dedicated ECDSA digital-signature peripheral for that part — only the RSA-flavoured one. Conversely the C6 does have a genuine, separate ECC accelerator block, which the S3 does not, despite both being marked as having ECC. Both distinctions are documented on the specifications page .

Deep-sleep figures generally. For the C61, H4 and S31, published deep-sleep numbers are Espressif estimates or are not yet published. They are labelled as estimates in the tables.

ESP32-S31 characterisation. Mass production began at the end of July 2026 and full power characterisation has not been published. Several figures on the S31 page come from the product page rather than a register-level datasheet.

Security advisory referenced

Espressif advisory AR2026-006 describes a Secure Boot bypass affecting the ROM-level ECDSA signature check on the ESP32-H2, C5, C61 and P4. Application-layer ECDSA verification through ESP-IDF is not affected. This is referenced on the affected variant pages and on the specifications page . Verify the advisory against your specific silicon revision with Espressif before relying on ROM-level Secure Boot as a root of trust.

Limitations of this site

Stated plainly:

  • Nothing here was measured. No chip was benchmarked, no current was metered, no board was tested for this site. It is a synthesis of published documentation, with community measurements cited where they exist and attributed to their authors.
  • Prices change. They were correct in September 2026 on Espressif’s public pages and are reference figures rather than quotations. Confirm with a distributor.
  • New silicon moves fast. Four of the fourteen parts documented here were announced or entered production within the last twelve months. Details for the H21, H4, E22 and S31 in particular will change as documentation matures.
  • Peripheral counts are approximate in the way datasheets are. “45 GPIOs” never means 45 usable pins: strapping pins, flash pins and memory-bus pins reduce the practical count, sometimes substantially. Always check the pin table for your specific package and memory configuration.

Corrections

If something here is wrong, the repository is the place to raise it. Corrections that cite a primary source are especially welcome, as are notes on where a figure here disagrees with silicon you have actually measured.

Attribution and trademarks

This is an independent reference. It is not affiliated with, endorsed by, sponsored by or reviewed by Espressif Systems.

ESP32, ESP8266, ESP-IDF and Espressif are trademarks of Espressif Systems (Shanghai) Co., Ltd. Matter, Thread and Zigbee are trademarks of their respective organisations. Bluetooth is a registered trademark of Bluetooth SIG, Inc. Wi-Fi is a registered trademark of Wi-Fi Alliance. Other product and company names are the property of their respective owners and are used here for identification only.

Content from artkeller/ESP32Features informed the peripheral-detail and security sections and is used under CC-BY-4.0 .