Espressif Systems · 2008 to today
The ESP32 family,
documented properly.
Fourteen system-on-chips, three CPU architectures, six radio protocols and a price band that starts at a dollar. This is a researched, source-cited reference to all of it — what each variant is actually for, what it costs, which board to buy, and how to choose.
- SoC variants
- 14
- Chips shipped
- 1 bn+
- Cheapest SoC
- $1.00
- Fastest core
- 500 MHz
What an ESP32 actually is
The ESP32 is not one chip. It is a family of low-cost microcontrollers with radios built in, designed by Espressif Systems in Shanghai. Every member pairs a 32-bit CPU, on-chip SRAM, a large peripheral set and hardware cryptography with at least one integrated wireless stack — usually Wi-Fi, Bluetooth LE, or 802.15.4 for Thread and Zigbee.
That combination is why the family became ubiquitous. Before the ESP8266 arrived in 2014, adding Wi-Fi to a hobby or low-volume commercial product meant a separate radio module costing more than the rest of the bill of materials. Espressif collapsed the microcontroller and the radio into a single part priced in dollars, then supported it with an open-source SDK. The ESP32 followed in September 2016 and became the default answer to "how do I put this device on the network?"
Ten years on, the family has split into clearly separated lines. The original ESP32 and the S-series are the general-purpose and multimedia workhorses. The C-series is the cost- and power-optimised RISC-V line. The H-series drops Wi-Fi entirely for ultra-low-power mesh networking. The P-series drops the radio instead and goes after high-performance displays and cameras. The newest E-series is not a microcontroller at all — it is a radio co-processor for a Linux host.
The lineup at a glance
Every current variant, grouped by the job it was designed for. Click through for the full specification, strengths and honest limitations of each.
The original and the S-series
General-purpose and multimedia parts. The original ESP32 and the S-series use Espressif's Xtensa cores; the brand-new S31 moves the line to RISC-V. This is where you go for lots of GPIO, displays, cameras and USB.
ESP32
ProductionThe original. Dual-core, Bluetooth Classic, Ethernet MAC.
- CPUDual-core Xtensa LX6
- Clock80–240 MHz
- SRAM520 KB
- RadioWi-Fi 4 + BT Classic/LE
- GPIO34
- Sleep~10 µA
ESP32-S2
ProductionWi-Fi only, native USB, lots of pins.
- CPUSingle-core Xtensa LX7
- Clock40–240 MHz
- SRAM320 KB + 16 KB RTC
- RadioWi-Fi 4 only
- GPIO43
- Sleep~5–7 µA
ESP32-S3
ProductionThe multimedia and edge-AI workhorse.
- CPUDual-core Xtensa LX7 with 128-bit SIMD
- Clock40–240 MHz
- SRAM512 KB + 16 KB RTC
- RadioWi-Fi 4 + BLE 5
- GPIO45
- Sleep~7 µA
ESP32-S31
ProductionEverything, in one part. RISC-V, Wi-Fi 6, gigabit Ethernet.
- CPUDual-core RISC-V with MMU, one core with a 128-bit SIMD data path
- ClockUp to 320 MHz (6.86 CoreMark/MHz)
- SRAM512 KB
- RadioWi-Fi 6 + BT 5.4 + 802.15.4 + 1 GbE
- GPIO60
- SleepNot yet published
The C-series
Cost- and power-optimised RISC-V parts. Small packages, small pin counts, modern radios and the lowest prices in the family. The volume workhorses for connected sensors and appliances.
ESP32-C2
ProductionThe floor. Minimal, tiny, cheapest in the family.
- CPUSingle-core RISC-V
- Clock20–120 MHz
- SRAM272 KB
- RadioWi-Fi 4 + BLE 5
- GPIO14
- Sleep<8 µA
ESP32-C3
ProductionThe dependable dollar chip.
- CPUSingle-core RISC-V
- Clock40–160 MHz
- SRAM400 KB
- RadioWi-Fi 4 + BLE 5
- GPIO22
- Sleep~5 µA
ESP32-C5
ProductionThe only ESP32 that speaks 5 GHz.
- CPUSingle high-performance RISC-V core
- Clock40–240 MHz
- SRAM384 KB + 16 KB LP
- RadioDual-band Wi-Fi 6 + BLE 5 + 802.15.4
- GPIO29
- Sleep~12 µA
ESP32-C6
ProductionThe modern default. Wi-Fi 6, Thread, Zigbee, PSA L2.
- CPUSingle high-performance RISC-V core
- Clock40–160 MHz
- SRAM512 KB + 16 KB LP
- RadioWi-Fi 6 + BLE 5.3 + 802.15.4
- GPIO30
- Sleep7 µA
ESP32-C61
ProductionWi-Fi 6 on a budget.
- CPUSingle-core RISC-V
- Clock40–160 MHz
- SRAM320 KB + 4 KB LP
- RadioWi-Fi 6 + BLE 5
- GPIO30
- Sleep~10 µA
The H-series
Wi-Fi removed on purpose. Bluetooth LE plus 802.15.4 for Thread, Zigbee and Matter, tuned for single-digit microamp sleep currents and years of battery life.
ESP32-H2
ProductionMesh specialist. No Wi-Fi, by design.
- CPUSingle-core RISC-V
- Clock32–96 MHz
- SRAM320 KB + 4 KB LP
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- GPIO19
- Sleep7 µA
ESP32-H21
SamplingThe H2, refined. 5 µA and 20 dBm.
- CPUSingle-core RISC-V
- ClockUp to 96 MHz
- SRAM320 KB + 128 KB ROM
- RadioBLE 5 + 802.15.4 (no Wi-Fi)
- GPIO19
- Sleep5 µA
ESP32-H4
SamplingDual-core low power with Bluetooth 5.4.
- CPUDual-core RISC-V
- ClockUp to 96 MHz
- SRAM384 KB (expandable PSRAM)
- RadioBLE 5.4 + 802.15.4 (no Wi-Fi)
- GPIO35
- Sleep~7 µA
The P-series
The radio removed instead. Raw application performance, MIPI display and camera interfaces, hardware video codecs and high-speed USB. Pair one with a C-series chip for connectivity.
The E-series
Not a microcontroller. A radio co-processor that hangs off a Linux host over PCIe, SDIO or USB and takes over the entire Wi-Fi and Bluetooth stack.
Pick a starting point
Nine times out of ten, one of these five answers is correct.
ESP32-C6
Wi-Fi 6, Bluetooth 5.3 and 802.15.4 in one part, with a low-power core and a PSA Level 2 security certification. The modern default for a connected device.
Chip from $1.85 · DevKit $9 Screens, cameras, audioESP32-S3
Dual 240 MHz cores with SIMD vector instructions, up to 16 MB of in-package PSRAM, USB OTG and 45 GPIOs. The one everybody uses for displays and on-device inference.
Chip from $1.85 · DevKit $15 Cheapest sensible optionESP32-C3
A single RISC-V core at 160 MHz with Wi-Fi and BLE 5 for a dollar. Mature, boring in the best sense, and supported by everything.
Chip from $1.00 · DevKit $8 Battery mesh nodesESP32-H2 / H21
No Wi-Fi at all — deliberately. Thread, Zigbee and BLE only, at 5–7 µA in deep sleep. For sensors that must run years on a coin cell.
Chip from $1.39 · DevKit $10 Serious HMIESP32-P4
400 MHz dual-core, MIPI-DSI and CSI, an image signal processor, hardware H.264 and 480 Mbps USB. No radio — pair it with a C6.
Chip from $4.00 · EV board $56 Not sure?Use the decision guide
A short set of questions — radio, power budget, display, GPIO count, certification — that narrows fourteen options down to one or two.
Read the guide →Explore the reference
History
From a Shanghai startup in 2008 to a billion chips shipped: the ESP8266 breakthrough, the 2016 launch, the STAR Market listing and the migration from Xtensa to RISC-V.
Variants
All fourteen SoCs side by side, plus a dedicated page for each with memory options, radios, peripherals, availability status and what it is genuinely bad at.
Specifications
The detail that datasheet summaries skip: USB speed classes, real SPI and I2S clocks, RMT channel architecture, deep-sleep currents and the hardware security matrix.
Pricing
Espressif's own reference prices for every chip, module and development kit, plus street prices for third-party boards and guidance on what actually drives BOM cost.
Boards & modules
Chip vs. module vs. dev board, the WROOM/WROVER/MINI/PICO naming scheme decoded, official kits, specialty AI boards and the third-party ecosystem.
Use cases
Fifty application categories with a recommended part for each — from smart plugs and Matter gateways to UVC webcams and predictive-maintenance nodes.
Ecosystem
ESP-IDF, Arduino, MicroPython, ESPHome, Rust and Zephyr — what each is good for, and a first-flash walkthrough that works on any variant.
Sources & method
Where every number on this site came from, which claims are vendor marketing, and where the published documentation contradicts itself.